Logic cell structure and integrated circuit with the logic cell structure

ABSTRACT

A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

PRIORITY CLAIM AND CROSS-REFERENCE

The present application is a continuation application of U.S. patentapplication Ser. No. 16/525,311 filed on Jul. 29, 2019, which isincorporated herein by reference in its entirety.

BACKGROUND

Typically, in the design of integrated circuits, standard cells havingfixed functions are pre-designed. The pre-designed standard cells arestored in cell libraries. When designing integrated circuits, thestandard cells are retrieved from the cell libraries and placed intodesired locations on an integrated circuit layout. During the cellplacement, the unit-row height layout system or the mixed-row heightssystem may be used. However, it is very challenging for the designer tobalance the cell delay and the placement density of logic cells in theunit-row height layout system or the mixed-row heights system.Therefore, a novel architecture of logic cell for improving the cellplacement problem in the layout system is highly desirable in the fieldof IC (Integrated circuit) design.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a diagram illustrating an electronic design automation systemin accordance with some embodiments.

FIG. 2 is a flowchart illustrating a method of designing and fabricatinga semiconductor-based circuit in accordance with some embodiments.

FIG. 3 is a diagram illustrating a cell library for storing logic cellsin accordance with some embodiments.

FIG. 4 is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 5A is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 5B is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 6A is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 6B is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 7 is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 8 is a diagram illustrating of a layout system of an integratedcircuit in accordance with some embodiments.

FIG. 9A is a diagram illustrating of a logic cell placed in a mixed-rowheights layout system in accordance with some embodiments.

FIG. 9B is a diagram illustrating of a logic cell placed in themixed-row heights layout system in accordance with some embodiments.

FIG. 9C is a diagram illustrating of a logic cell placed in themixed-row heights layout system in accordance with some embodiments.

FIG. 9D is a diagram illustrating a schematic circuit of a logic cell inaccordance with some embodiments.

FIG. 9E is a diagram illustrating a schematic circuit of a logic cell inaccordance with some embodiments.

FIG. 10 is a diagram illustrating a plurality of cell structures of alogic cell in accordance with some embodiments.

FIG. 11 is a flowchart illustrating a placement method in accordancewith some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1 is a diagram illustrating an electronic design automation system100 in accordance with some embodiments. As shown in FIG. 1, system 100includes an electronic design automation (“EDA”) tool 110 having a placeand route tool including a chip assembly router 120.

The EDA tool 110 is a special purpose computer formed by retrievingstored program instructions 136 from a computer readable storage medium130, 140 and executing the instructions on a general purpose processor114. Processor 114 may be any central processing unit (“CPU”),microprocessor, micro-controller, or computational device or circuit forexecuting instructions. The non-transitory machine readable storagemedium 130, 140 may be a flash memory, random access memory (“RAM”),read only memory (“ROM”), or other storage medium. Examples of RAMsinclude, but are not limited to, static RAM (“SRAM”) and dynamic RAM(“DRAM”). ROMs include, but are not limited to, programmable ROM(“PROM”), electrically programmable ROM (“EPROM”), and electricallyerasable programmable ROM (“EEPROM”), to name a few possibilities.

System 100 may include a display 116 and a user interface or inputdevice 112 such as, for example, a mouse, a touch screen, a microphone,a trackball, a keyboard, or other device through which a user may inputdesign and layout instructions to system 100. The one or more computerreadable storage mediums 130, 140 may store data input by a user such asa circuit design and cell information 132, which may include a celllibrary 132 a, design rules 134, one or more program files 136, and oneor more graphical data system (“GDS”) II files 142.

EDA tool 110 may also include a communication interface 118 allowingsoftware and data to be transferred between EDA tool 110 and externaldevices. Examples of a communications interface 118 include, but are notlimited to, a modem, an Ethernet card, a wireless network card, aPersonal Computer Memory Card International Association (“PCMCIA”) slotand card, or the like. Software and data transferred via communicationsinterface 118 may be in the form of signals, which may be electronic,electromagnetic, optical, or the like that are capable of being receivedby communications interface 118. These signals may be provided tocommunications interface 118 via a communications path (e.g., achannel), which may be implemented using wire, cable, fiber optics, atelephone line, a cellular link, a radio frequency (“RF”) link and othercommunication channels. The communications interface 118 may be a wiredlink and/or a wireless link coupled to a local area network (LAN) or awide area network (WAN).

Router 120 is capable of receiving an identification of a plurality ofcells to be included in a circuit layout, including a list 132 of pairsof cells, selected from the cell library 132 a, within the plurality ofcells to be connected to each other. Design rules 134 may be used for avariety of processing technologies. In some embodiments, the designrules 134 configure the router 120 to locate connecting lines and viason a manufacturing grid. Other embodiments may allow the router toinclude off-grid connecting lines and/or vias in the layout.

FIG. 2 illustrates one example of a method 200 of designing andfabricating a semiconductor-based circuit. In operation 202, agate-level netlist is developed or extracted. As will be understood byone of ordinary skill in the art, the gate-level netlist can beextracted from circuit schematic by processor 114 of system 100.

In operation 204, floor planning for the semiconductor circuit isperformed by system 100. In some embodiments, floor planning includesdividing a circuit into functional blocks, which are portions of thecircuit, and identifying the layout for these functional blocks.

In operation 206, power planning for the semiconductor circuit isperformed by system 100. Power planning includes identifying the powerlayout for the functional blocks of the semiconductor circuit. Forexample, the conductive traces for routing power and ground on thevarious conductive layers of the semiconductor circuit.

In operation 208, system 100 performs placement for the semiconductorcircuit. According to some embodiments, the circuit placement includesdetermining the placement for the electronic components, circuitry, andlogic elements. For example, the placement of the transistors,resistors, inductors, logic gates, and other elements of thesemiconductor circuit are selected in operation 208.

In operation 210, system 100 performs power-grid enhancement.

In operation 212, the routings for the devices and semiconductor circuitare mapped. Routing in operation 212 is performed by router 120 ofsystem 100.

In operation 214, a data file, such as a graphic database system (“GDS”)II file, including data representing the physical layout of the circuitis generated and stored in a non-transient machine readable storage 140.As will be understood by one of ordinary skill in the art, the data fileis used by mask making equipment, such as an optical pattern generator,to generate one or more masks for the circuit.

In operation 216, one or more masks for the semiconductor circuit arecreated based on the data file stored in operation 214. Once thephysical design layout is generated, the physical design may be sent toa manufacturing tool to generate photolithographic masks that may beused for fabricating the semiconductor circuit. The physical designlayout may be sent to the manufacturing tool through the LAN/WAN orother suitable forms of transmission from the EDA to the manufacturingtool.

According to some embodiments, the operations 208˜212 may be an APR(Automatic Place and Route) process. During the APR process, a layout ofthe semiconductor circuit (i.e. integrated circuit, IC) is generatedautomatically by the APR process by using the plurality of proposedstandard cells or logic cells. A logic cell may represent a singlefunctional block of logic. A standard cell for example may represent aNAND gate, NOR gate, flip flop, AND gate, OR gate, XOR gate, XNOR gate,inverter, latch, or the like. The logic cell enables an integratedcircuit designer to utilize a library of cells as reusable buildingblocks for an integrated circuit without the need to separately designeach block of logic represented by a cell. The logic cells may beincluded in a library of cells for use by integrated circuit designers.

FIG. 3 is a diagram illustrating a cell library 302 for storing logiccells in accordance with some embodiments. The cell library 302 may be astandard cell library. The logic cells may be standard cells, and thelogic cells may be applied into cell rows of a layout of a semiconductorcircuit during the operations 208˜212 or the APR process. A logic cellis arranged to perform a specific logical function. For example, thespecific logical function may be the operation of NAND, NOR, flip flop,AND, OR, XOR, XNOR, inverting, latching, or the like. The logic cellsmay have different cell structures. According to some embodiments, thelogic cells may be implemented with a plurality of cell structures 304,306, 308, 310, 312, and 314. It is noted that the present disclosure isnot limited by those cell structures. The logic cells may be configuredto have other type of cell structures.

According to some embodiments, the cell structure 304 may be a standardcell structure with a first cell height S. The cell structure 306 may bea second standard cell structure with a second cell height T. The cellheight T is greater than the cell height S. The widths of the cellstructure 304 and 306 are W_a and W_b respectively. According to someembodiments, the cell heights S and T may be constant heights and thewidths W_a and W_b may be a variable width. However, this is not alimitation of the present disclosure. In another embodiment, the cellheights S and T may be variable heights and the widths W_a and W_b maybe a constant width.

The cell structure 308 may be a third standard cell structure having afirst portion 308 a with the height S, a second portion 308 b with theheight S, and a third portion 308 c with the height T1. The firstportion 308 a and the second portion 308 b are separated by the thirdportion 308 c. According to some embodiments, the upper boundary (i.e.B1) of the third portion 308 c is abutted against a lower boundary ofthe first portion 308 a, and a lower boundary (i.e. B2) of the thirdportion 308 c is abutted against the upper boundary of the secondportion 308 b. The width of the cell structure 308 is W_c. The height T1is substantially equal to the height T of the standard cell structure306. The cell heights S and T1 may be constant heights and the width W_cmay be a variable width. According to some embodiments, the firstportion 308 a, the second portion 308 b, and the third portion 308 c maybe formed within a bounding box 308 d of the cell structure 308. Thewidth of the bounding box 308 d is W_c, and the height of the boundingbox 308 d is the total of the heights (i.e. 2*S+T1) of the first portion308 a, the second portion 308 b, and the third portion 308 c. The firstportion 308 a, the second portion 308 b, and the third portion 308 c maybe arranged to be a rectangular structure, and the rectangular structuremay overlap with the bounding box 308 d. According to some embodiments,the first portion 308 a and the second portion 308 b may comprisesemiconductor elements or active devices, e.g. transistors, and thethird portion 308 c may comprise the interconnecting paths for couplingthe semiconductor elements in the first portion 308 a and the activedevices in the second portion 308 b. The semiconductor elements may bethe front-end-of-line (FEOL) in the semiconductor device, and theinterconnecting paths may be the back-end-of-line (BEOL) in thesemiconductor device.

According to some embodiments, the height T1 of the third portion 308 cmay be greater than the height T. The height T1 may be a total of n*Tand m*S, wherein n is an integer not less than 2, and m is an integernot less than 1. For example, the height T1 may be a total of 2*T and1*S. In this example, the height T1 is substantially equal to a total ofthe heights T of two standard cell structure 306 and the height of onestandard cell structure 304.

The cell structure 310 may be a fourth standard cell structure having afirst portion 310 a with the height T, a second portion 310 b with theheight T, and a third portion 310 c with the height S1. The firstportion 310 a and the second portion 310 b are separated by the thirdportion 310 c. According to some embodiments, the upper boundary (i.e.B3) of the third portion 310 c is abutted against a lower boundary ofthe first portion 310 a, and a lower boundary (i.e. B4) of the thirdportion 310 c is abutted against the upper boundary of the secondportion 310 b. The width of the cell structure 310 is W_d. The height S1is substantially equal to the height S of the standard cell structure304. The cell heights T and S1 may be constant heights and the width W_dmay be a variable width. According to some embodiments, the firstportion 310 a, the second portion 310 b, and the third portion 310 c maybe formed within a bounding box 310 d of the cell structure 310. Thewidth of the bounding box 310 d is W_d, and the height of the boundingbox 310 d is the total of the heights (i.e. 2*T+S1) of the first portion310 a, the second portion 310 b, and the third portion 310 c. The firstportion 310 a, the second portion 310 b, and the third portion 310 c maybe arranged to be a rectangular structure, and the rectangular structuremay overlap with the bounding box 310 d. According to some embodiments,the first portion 310 a and the second portion 310 b may comprisesemiconductor elements, e.g. transistors, and the third portion 310 cmay comprise the interconnecting paths for coupling the semiconductorelements in the first portion 310 a and the semiconductor elements inthe second portion 310 b.

According to some embodiments, the height S1 of the third portion 310 cmay be greater than the height S. The height S1 may be a total of n*Sand m*T, wherein n is an integer not less than 2, and m is an integernot less than 1. For example, the height S1 may be a total of 2*S and1*T. In this example, the height S1 is substantially equal to a total ofthe heights S of two standard cell structure 304 and the height of onestandard cell structure 306.

The cell structure 312, which may be a rectilinear dual-driver cellstructure, comprises a first portion 312 a with the height S and thewidth W_e, a second portion 312 b with the height S and the width W_e,and a third portion 312 c. The width W_e of the first portion 312 a maybe different to the width W_e of the second portion 312 b. A distancebetween the first portion 312 a and the second portion 312 b in verticaldirection is T2. A distance between the first portion 312 a and thesecond portion 312 b in horizontal direction is D1. The distance T2 issubstantially equal to the height T of the standard cell structure 306.The heights S and T2 may be constant heights and the widths W_e and D1may be variable widths. According to some embodiments, the first portion312 a, the second portion 312 b, and the third portion 312 c may beformed within a bounding box 312 d of the cell structure 312. The widthof the bounding box 312 d is W, and the height of the bounding box 312 dis H1. According to some embodiments, the width W1 is not less than atotal of the width W_e of the first portion 312 a, the width W_e of thesecond portion 312 b, and the distance D1. The height H1 is not lessthan a total of the height S of the first portion 312 a, the height S ofthe second portion 312 b, and the distance T2. According to someembodiments, the bounding box 312 d has a rectangular boundary, and thefirst portion 312 a and the second portion 312 b may be located on thediagonal direction of the bounding box 312 d. However, this is not alimitation of the present embodiments. The bounding box 312 d may be apolygonal bounding box surrounding the first portion 312 a, the secondportion 312 b, and the third portion 312 c. According to someembodiments, the first portion 312 a and the second portion 312 b maycomprise semiconductor elements, e.g. transistors, and the third portion312 c may comprise the interconnecting paths for connecting thesemiconductor elements in the first portion 312 a and the semiconductorelements in the second portion 312 b.

According to some embodiments, the distance T2 may be greater than theheight T. The distance T2 may be a total of n*T and m*S, wherein n is aninteger not less than 2, and m is an integer not less than 1. Forexample, the distance T2 may be a total of 2*T and 1*S. In this example,the distance T2 is substantially equal to a total of the heights T oftwo standard cell structure 306 and the height of one standard cellstructure 304.

The cell structure 314, which may be a rectilinear dual-driver cellstructure, comprises a first portion 314 a with the height T and thewidth W_f, a second portion 314 b with the height T and the width W_f,and a third portion 314 c. The width W_f of the first portion 314 a maybe different to the width W_f of the second portion 314 b. A distancebetween the first portion 314 a and the second portion 314 b in verticaldirection is S2. A distance between the first portion 314 a and thesecond portion 314 b in horizontal direction is D2. The distance S2 issubstantially equal to the height S of the standard cell structure 304.The heights T and S2 may be constant heights and the widths W_f and D2may be variable widths. According to some embodiments, the first portion314 a, the second portion 314 b, and the third portion 314 c may beformed within a bounding box 314 d of the cell structure 314. The widthof the bounding box 314 d is W2, and the height of the bounding box 314d is H2. According to some embodiments, the width W2 is not less than atotal of the width W_f of the first portion 314 a, the width W_f of thesecond portion 314 b, and the distance D2. The height H2 is not lessthan a total of the height T of the first portion 314 a, the height T ofthe second portion 314 b, and the distance S2. According to someembodiments, the bounding box 314 d is a rectangular boundary, and thefirst portion 314 a and the second portion 314 b may be located on thediagonal direction of the bounding box 314 d. However, this is not alimitation of the present embodiments. The bounding box 314 d may be apolygonal bounding box surrounding the first portion 314 a, the secondportion 314 b, and the third portion 314 c. According to someembodiments, the first portion 314 a and the second portion 314 b maycomprise semiconductor elements, e.g. transistors, and the third portion314 c may comprise the interconnecting paths for connecting thesemiconductor elements in the first portion 314 a and the semiconductorelements in the second portion 314 b.

According to some embodiments, the distance S2 may be greater than theheight S. The distance S2 may be a total of n*S and m*T, wherein n is aninteger not less than 2, and m is an integer not less than 1. Forexample, the distance S2 may be a total of 2*S and 1*T. In this example,the distance S2 is substantially equal to a total of the heights S oftwo standard cell structure 304 and the height of one standard cellstructure 306.

FIG. 4 is a diagram illustrating of a layout system 400 of an integratedcircuit (or a semiconductor device) in accordance with some embodiments.The layout system 400 may be a mixed-row heights layout system. Thelayout system 400 comprises a plurality of first-type doped rows 402a-402 d with a first row height, i.e. S, for each row and a plurality ofsecond-type doped rows 404 a-404 d with a second row height, i.e. T, foreach row. The first-type doped rows 402 a-402 d are arranged to beinterleaved with the second-type doped rows 404 a-404 d. For example,the upper edge (i.e. E1) of the first-type doped row 402 a abuts againstthe lower edge of the second-type doped row 404 a, the upper edge (i.e.E2) of the second-type doped row 404 b abuts against the lower edge ofthe first-type doped row 402 a, the upper edge (i.e. E3) of thefirst-type doped row 402 b abuts against the lower edge of thesecond-type doped row 404 b, and so on. Moreover, each of the first-typedoped rows 402 a-402 d may comprise n-type well(s) and/or p-typesubstrate(s), and each of the second-type doped rows 404 a-404 d maycomprise n-type well(s) and/or p-type substrate(s).

As the row height T of the second-type doped rows 404 a-404 d is greaterthan the row height S of the first-type doped rows 402 a-404 d, thesecond-type doped rows 404 a-404 d may be configured to have relativelyhigh speed transistors (or semiconductor elements), and the first-typedoped rows 402 a-402 d may be configured to have relatively low speedtransistors.

According to some embodiments, a logic cell 402 with the cell structure304 may be placed on the first-type doped rows 402 d. A logic cell 404with the cell structure 306 may be placed on the second-type doped rows404 c.

A logic cell 406 with the cell structure 308 may be placed on twofirst-type doped rows 402 a, 402 b, and one second-type doped row 404 b.The first-type doped rows 402 a, 402 b, and the second-type doped row404 b may be three consecutive rows in the layout system 400.Specifically, the first portion 308 a of the cell structure 308 may bedisposed on the first-type doped row 402 a, the second portion 308 b ofthe cell structure 308 may be disposed on the other first-type doped row402 b, and the third portion 308 c of the cell structure 308 may bedisposed on the second-type doped row 404 b. The cell structure 308 maybe regarded as a jump-row cell structure, i.e. the first portion 308 aand the second portion 308 b jump over or bridge over the second-typedoped row 404 b. In the first-type doped rows 402 a and 402 b, the firstportion 308 a and the second portion 308 b of the logic cell 406 areconfigured to have the relatively low transistors, and in thesecond-type doped row 404 b, the third portion 308 c of the logic cell406 is configured to be the interconnecting paths between the relativelylow transistors in the first portion 308 a and the second portion 308 b.According to some embodiments, the third portion 308 c is arranged tobridge over the second-type doped row 404 b or the logic cell placed inthe second-type doped row 404 b.

A logic cell 408 with the cell structure 310 may be placed on twosecond-type doped rows 404 a, 404 b, and one first-type doped row 402 a.The second-type doped rows 404 a, 404 b, and the first-type doped row402 a may be three consecutive rows in the layout system 400.Specifically, the first portion 310 a of the cell structure 310 may bedisposed on the second-type doped row 404 a, the second portion 310 b ofthe cell structure 310 may be disposed on the other second-type dopedrow 404 b, and the third portion 310 c of the cell structure 310 may bedisposed on the first-type doped row 402 a. The cell structure 310 maybe regarded as a jump-row cell structure, i.e. the first portion 310 aand the second portion 310 b jump over or bridge over the first-typedoped row 402 a. In the second-type doped rows 404 a and 404 b, thefirst portion 310 a and the second portion 310 b of the logic cell 408are configured to have the relatively high transistors, and in thefirst-type doped row 402 a, the third portion 310 c of the logic cell408 is configured to be the interconnecting paths between the relativelyhigh transistors in the first portion 310 a and the second portion 310b. According to some embodiments, the third portion 310 c is arranged tobridge over the first-type doped row 402 a or the logic cell placed inthe first-type doped row 402 a.

In addition, a logic cell 410 with a cell structure crossing afirst-type doped row 402 d and a second-type doped row 404 d and a logiccell 412 with a cell structure crossing a first-type doped row 402 c andtwo second-type doped rows 404 c and 404 d may be placed on the layoutsystem 400. The detailed description of the logic cells 410 and 412 isomitted here for brevity.

FIG. 5A is a diagram illustrating of a layout system 500 a of anintegrated circuit in accordance with some embodiments. FIG. 5B is adiagram illustrating of a layout system 500 b of an integrated circuitin accordance with some embodiments. In FIG. 5A, the layout system 500 amay be a mixed-row heights layout system. The layout system 500 acomprises a plurality of first-type doped rows 502 a-502 d with thefirst row height S for each row and a plurality of second-type dopedrows 504 a-504 d with the second row height T for each row.

According to some embodiments, a plurality of relatively low speed logiccells 506 a-506 e may be placed on the first-type doped rows 502 a-502 drespectively, and a plurality of relatively high speed logic cells 508a-508 f may be placed on the second-type doped rows 504 a-504 drespectively. The number and the size of the logic cells 506 a-506 e maybe different from the number and the size of the logic cells 508 a-508f. Therefore, after the cell placement operation, the usage of thefirst-type doped rows 502 a-502 d and the second-type doped rows 504a-504 d may be unbalanced. For example, the usage rate of the first-typedoped rows 502 a-502 d may be 30% while the usage rate of thesecond-type doped rows 504 a-504 d may be 70%. The unused spaces, e.g.510 a-510 c, in the first-type doped rows 502 a-502 d are wasted but thearea is still counted for the layout system 500 a. To increase the usagerate of the first-type doped rows 502 a-502 d, the logic cells with thecell structure 308 may be placed in the spaces 510 a-510 c of thefirst-type doped rows 502 a-502 d as shown in FIG. 5B.

In comparison to the layout system 500 a, the layout system 500 b inFIG. 5B further comprises a logic cells 512 and 514. The logic cell 512is configured to be the cell structure 308, and the logic cell 512comprises a first portion 512 a, a second portion 512 b, and a thirdportion 512 c. The first portion 512 a is disposed in the space 510 a ofthe first-type doped row 502 a, the second portion 512 b is disposed inthe space 510 b of the first-type doped row 502 b, and the third portion512 c is disposed in the second-type doped row 504 b and is overlappedwith a portion of the logic cell 508 c. According to some embodiments,the third portion 512 c is arranged to be the interconnecting paths ofthe first portion 512 a and the second portion 512 b and is formed inthe BEOL of the semiconductor device, and the first portion 512 a andthe second portion 512 b are arranged to be the semiconductor elementsformed in the FEOL of the semiconductor device. Therefore, the thirdportion 512 c may be arranged to overlap with a portion of the logiccell 508 c viewing from the top of the semiconductor device.

In addition, the logic cell 514 is also configured to be the cellstructure 308 comprising a first portion 514 a, a second portion 514 b,and a third portion 514 c, wherein the first portion 514 a is disposedin the space 510 b of the first-type doped row 502 b, the second portion514 b is disposed in the space 510 c of the first-type doped row 502 c,and the third portion 514 c is disposed in the second-type doped row 504c and is overlapped with a portion of the logic cell 508 e. The thirdportion 514 c is arranged to be the interconnecting paths of the firstportion 514 a and the second portion 514 b and is formed in the BEOL ofthe semiconductor device, and the first portion 514 a and the secondportion 514 b are arranged to be the semiconductor elements formed inthe FEOL of the semiconductor device. Therefore, the third portion 514 cmay be arranged to overlap with a portion of the logic cell 508 eviewing from the top of the semiconductor device.

Accordingly, the spaces 510 a-510 c in the first-type doped rows 502a-502 d may be reused by the logic cells 512 and 514 with the cellstructure 308 such that the usage rate of the first-type doped rows 502a-502 d in the layout system 500 b may be increased. Moreover, when theactive devices, e.g. transistors, in the first portion 512 a and thesecond portion 512 b of the logic cell 512 are placed in the same typeof doped rows (i.e. the first-type doped rows 502 a and 502 b), thetransistors in the first portion 512 a and the transistors in the secondportion 512 b may have equal speed such that the signal delay of thelogic cell 512 (as well as the circuit 514) may be balanced andoptimized.

FIG. 6A is a diagram illustrating of a layout system 600 a of anintegrated circuit in accordance with some embodiments. FIG. 6B is adiagram illustrating of a layout system 600 b of an integrated circuitin accordance with some embodiments. The layout system 600 a comprises aplurality of first-type doped rows 602 a-602 d with the first row heightS for each row and a plurality of second-type doped rows 604 a-604 dwith the second row height T for each row.

According to some embodiments, a plurality of relatively low speed logiccells 606 a-606 e may be placed on the first-type doped rows 602 a-602 drespectively, and a plurality of relatively high speed logic cells 608a-608 d may be placed on the second-type doped rows 604 a-604 drespectively. After the cell placement operation, the usage of thefirst-type doped rows 602 a-602 d and the second-type doped rows 604a-604 d may be unbalanced. For example, the unused spaces, e.g. 610a-610 b, in the second-type doped rows 604 a-604 b are wasted but thearea is still counted for the layout system 600 a. To increase the usagerate of the second-type doped rows 604 a-604 d, the logic cells with thecell structure 310 may be placed in the spaces 610 a-610 b of thesecond-type doped rows 604 a-604 b as shown in FIG. 6B.

In comparison to the layout system 600 a, the layout system 600 b inFIG. 6B further comprises a logic cell 612. The logic cell 612 isconfigured to be the cell structure 310, and the logic cell 612comprises a first portion 612 a, a second portion 612 b, and a thirdportion 612 c. The first portion 612 a is disposed in the space 610 a ofthe second-type doped row 604 a, the second portion 612 b is disposed inthe space 610 b of the second-type doped row 604 b, and the thirdportion 612 c is disposed in the first-type doped row 602 a and isoverlapped with a portion of the logic cell 606 a. According to someembodiments, the third portion 612 c is arranged to be theinterconnecting paths of the first portion 612 a and the second portion612 b and is formed in the BEOL of the semiconductor device, and thelogic cell 606 a and the second portion 612 b are arranged to be thesemiconductor elements formed in the FEOL of the semiconductor device.Therefore, the third portion 612 c may be arranged to overlap with aportion of the logic cell 606 a viewing from the top of thesemiconductor device.

Accordingly, the spaces 610 a-610 b in the second-type doped rows 604a-604 b may be reused by the logic cell 612 with the cell structure 310such that the usage rate of the second-type doped rows 604 a-604 d inthe layout system 600 b may be increased. Moreover, when the activedevices, e.g. transistors, in the first portion 612 a and the secondportion 612 b of the logic cell 612 are placed in the same type of dopedrows (i.e. the second-type doped rows 604 a and 604 b), the transistorsin the first portion 612 a and the transistors in the second portion 612b may have equal speed such that the signal delay of the logic cell 612may be balanced and optimized.

FIG. 7 is a diagram illustrating of a layout system 700 of an integratedcircuit in accordance with some embodiments. For brevity, the numeralsof elements in the layout system 700 are similar to the numerals ofelements in the layout system 500 b.

In comparison to the layout system 500 b, the layout system 700 in FIG.7 further comprises a logic cell 702. The logic cell 702 is configuredto be the cell structure 312, and the logic cell 702 comprises a firstportion 702 a, a second portion 702 b, and a third portion 702 c. Thefirst portion 702 a is disposed in the space 510 d of the first-typedoped row 502 c, the second portion 702 b is disposed in the space 510 fof the first-type doped row 502 d, and the third portion 702 c isdisposed in a portion of the second-type doped row 504 c, the first-typedoped row 502 c, the second-type doped row 504 d, and the first-typedoped row 502 d. The space 510 d and the space 510 f are rectilinearspaces. According to some embodiments, the third portion 702 c isarranged to be the interconnecting paths of the first portion 702 a andthe second portion 702 b and is formed in the BEOL of the semiconductordevice, and the logic cell 508 e, the logic cell 506 c, the logic cell508 f, and the logic cell 506 d are arranged to be the semiconductorelements formed in the FEOL of the semiconductor device. Therefore, thethird portion 702 c are formed above a portion of the logic cell 508 e,the logic cell 506 c, a portion of the logic cell 508 f, and the logiccell 506 d, and may be overlapped with the portion of the logic cell 508e, the logic cell 506 c, the portion of the logic cell 508 f, and thelogic cell 506 d viewing from the top of the semiconductor device.

Accordingly, the spaces 510 d-510 f in the first-type doped rows 502c-502 d may be reused by the logic cell 702 with the cell structure 312such that the usage rate of the first-type doped rows 502 a-502 d in thelayout system 700 may be increased. Moreover, the resource of the layoutsystem 700 may be increased by placing the rectilinear cell structures312 into the rectilinear space fragments.

FIG. 8 is a diagram illustrating of a layout system 800 of an integratedcircuit in accordance with some embodiments. For brevity, the numeralsof elements in the layout system 800 are similar to the numerals ofelements in the layout system 600 a.

In comparison to the layout system 600 a, the layout system 800 in FIG.8 further comprises a logic cell 802. The logic cell 802 is configuredto be the cell structure 314, and the logic cell 802 comprises a firstportion 802 a, a second portion 802 b, and a third portion 802 c. Thefirst portion 802 a is disposed in the space 610 a of the second-typedoped row 604 a, the second portion 802 b is disposed in the space 610 cof the second-type doped row 604 b, and the third portion 802 c isdisposed in the second-type doped row 604 a, the first-type doped row602 a, the second-type doped row 604 b, and a portion of the first-typedoped row 602 b. The space 610 a and the space 610 c are rectilinearspaces. According to some embodiments, the third portion 802 c isarranged to be the interconnecting paths of the first portion 802 a andthe second portion 802 b and is formed in the BEOL of the semiconductordevice, and the logic cell 608 a, the logic cell 606 a, the logic cell608 b, and the logic cell 606 b are arranged to be the semiconductorelements formed in the FEOL of the semiconductor device. Therefore, thethird portion 802 c are formed above a portion of the logic cell 608 a,a portion of the logic cell 606 a, the logic cell 608 b, and a portionof the logic cell 606 b, and may be overlapped with the portion of thelogic cell 608 a, the portion of the logic cell 606 a, the logic cell608 b, and the portion of the logic cell 606 b viewing from the top ofthe semiconductor device.

Accordingly, the spaces 610 a and 610 c in the second-type doped rows604 a-604 b may be reused by the logic cell 802 with the cell structure314 such that the usage rate of the second-type doped rows 604 a-604 din the layout system 800 may be increased. Moreover, the resource of thelayout system 800 may be increased by placing the rectilinear cellstructures 314 into the rectilinear space fragments.

FIG. 9A is a diagram illustrating of a logic cell 902 placed in amixed-row heights layout system 900 in accordance with some embodiments.The logic cell 902 is configured to be the cell structure 306 and isplaced on the second-type doped row 904 in the mixed-row heights layoutsystem 900. During the cell placement operation, the cell structure ofthe logic cell 902 may be replaced with a logic cell 910 with the cellstructure 308 or a logic cell 912 with the cell structure 312 from thecell structure 306 to increase the usage of the first-type doped rows906 and 908. FIG. 9B is a diagram illustrating of the logic cell 910placed in the mixed-row heights layout system 900 in accordance withsome embodiments. When the logic cell 902 is replaced with the logiccell 910, the logic cell 902 may be re-configured into two portions,i.e. 910 a and 910 b. The two portions 910 a and 910 b may be placed inthe first-type doped rows 906 and 908 respectively. The logic cell 910is similar to the above mentioned logic cell 702, thus the detaileddescription of the logic cell 910 is omitted here for brevity.

FIG. 9C is a diagram illustrating of the logic cell 912 placed in themixed-row heights layout system 900 in accordance with some embodiments.When the logic cell 902 is replaced with the logic cell 912, the logiccell 902 may be re-configured into two portions, i.e. 912 a and 912 b.The two portions 912 a and 912 b may be placed in the first-type dopedrows 906 and 908 respectively. The logic cell 912 is similar to theabove mentioned logic cell 512 or 514, thus the detailed description ofthe logic cell 912 is omitted here for brevity.

FIG. 9D is a diagram illustrating a schematic circuit of the logic cell902 in accordance with some embodiments. The schematic circuit of thelogic cell 902 may comprise an AND gate (or NAND gate) having two inputterminals Ni1 and Ni2 and an output terminal No. When the logic cell 902is re-configured into the logic cell 910 or 912, the schematic circuitof the logic cell 902 may be re-configured into the schematic circuit asshown in FIG. 9E. FIG. 9E is a diagram illustrating a schematic circuitof the logic cell 910 (or 912) in accordance with some embodiments. Theschematic circuit of the logic cell 910 comprises two AND gates AND1 andAND2. In other words, the logic cell 902 is re-configured intodual-driver cells. The first input terminal of the AND gate AND1 and thefirst input terminal of the AND gate AND2 are coupled to the inputterminal Ni1, the second input terminal of the AND gate AND1 and thesecond input terminal of the AND gate AND2 are coupled to the inputterminal Ni2, and the output terminal of the AND gate AND1 and theoutput terminal of the AND gate AND2 are coupled to the output terminalNo. The logical function of the logic cell 910 is similar to the logicalfunction of the logic cell 902. However, due to the dual-driverstructure, the routing paths of the logic cell 910 may greater than therouting paths of the logic cell 902. According to some embodiments, thefirst portion 910 a and the second portion 910 b may be the layout cellof the AND gate AND1 and the AND gate AND2 respectively. The thirdportion 910 c may be the layout portion of the interconnecting pathsbetween the AND gate AND1 and the AND gate AND2.

FIG. 10 is a diagram illustrating a plurality of cell structures 1002 a,1002 b, 1002 c, 1002 d, 1002 e, and 1002 f of a logic cell (e.g. a NANDgate) in accordance with some embodiments. The cell structures 1002 amay be the cell structure 304. The cell structures 1002 b may be thecell structure 308. The cell structures 1002 c may be the cell structure306. The cell structures 1002 d may be a cell structure having a firstportion disposed in the first-type doped row and a second portiondisposed in the second-type doped row. The cell structures 1002 e may bethe cell structure 310. The cell structures 1002 f may be the cellstructure 314 (or 312). According to some embodiments, the NAND gatewith the cell structure 1002 a may have the largest signal delay, andthe NAND gate with the cell structure 1002 e may have the smallestsignal delay. In other words, the NAND gate with the cell structure 1002a may have the lowest operating speed, and the NAND gate with the cellstructure 1002 e may have the highest operating speed. The signal delayof the NAND gate with the cell structure 1002 b may be closed to thesignal delay of the NAND gate with the cell structure 1002 c. The signaldelay of the NAND gate with the cell structure 1002 f may be slightlysmaller than the signal delay of the NAND gate with the cell structure1002 e. For example, when the signal delays of the cell structures 1002a, 1002 b, 1002 c, 1002 d, 1002 e, and 1002 f of the NAND gates are T1,T2, T3, T4, T5, and T6 respectively, the relationship of the signaldelays T1, T2, T3, T4, T5, and T6 may be expressed as below:

T1>T2≈T3>T4>T6>T5

In addition, for the NAND gates with the cell structures 1002 b, 1002 e,and 1002 f, the interconnecting paths or the post-connection wires usedfor connecting the different portions of the cell structure may costadditional area for the cell structure. For example, when the areas ofthe cell structures 1002 a, 1002 b, 1002 c, 1002 d, 1002 e, and 1002 fof the NAND gates are A1, A2, A3, A4, A5, and A6 respectively, therelationship of the areas A1, A2, A3, A4, A5, and A6 may be expressed asbelow:

A6>A5>A4>A2>A3>A1

FIG. 11 is a flowchart illustrating a placement method 1100 inaccordance with some embodiments. The placement method 1100 may balancethe placement density of a mixed-row heights layout system of anintegrated circuit. The placement method 1100 comprises operations1102-1108. Provided that substantially the same result is achieved, theoperations of the flowchart shown in FIG. 11 may not follow the sameorder and may not be contiguous. In some embodiments, other intermediateoperations may be included.

In operation 1102, a plurality of cell circuits with a plurality of cellstructures are placed in the mixed-row heights layout system (e.g. 500a) having a plurality of first-type doped rows interleaved with aplurality of second-type doped rows. The plurality of cell structuresmay be the above mentioned cell structures 304, 306, 412, and 1002 d.

In operation 1104, a measuring operation is performed upon the mixed-rowheights layout system to determine if the density of the first-typedoped rows is greater than the density of the second-type doped rows inthe mixed-row heights layout system. If the density of the first-typedoped rows is greater than the density of the second-type doped rows,goes to operation 1106. If the density of the second-type doped rows isgreater than the density of the first-type doped rows, goes to operation1108.

In operation 1106, a first adjusting operation is performed upon themixed-row heights layout system. During the first adjusting operation, anumber or a partial of the logic cells with the cell structure 304 arere-configured into the cell structure 306, 310, and/or 314. For example,when the usage rate of the first-type doped rows is 80% and the usagerate of the second-type doped rows is 20%, the first adjusting operationmay change 30% of the logic cells (e.g. the logic cells with the cellstructure 304) in the first-type doped rows into the second-type dopedrows (e.g. the logic cells with the cell structures 306, 310, and/or314). After the first adjusting operation, the speed of there-configured logic cells is increased, and the overall performance ofthe semiconductor device is upgraded. The balancing of the usage of thefirst-type doped rows and the second-type doped rows is also improved.

In operation 1108, a second adjusting operation is performed upon themixed-row heights layout system. During the second adjusting operation,a number or a partial of the logic cells with the cell structure 306 arere-configured into the cell structure 304, 308, and/or 312. For example,when the usage rate of the second-type doped rows is 80% and the usagerate of the first-type doped rows is 20%, the second adjusting operationmay change 30% of the logic cells (e.g. the logic cells with the cellstructure 306) in the second-type doped rows into the first-type dopedrows (e.g. the logic cells with the cell structures 304, 308, and/or312).

For another example, in operation 1108, when the usage rate of thesecond-type doped rows is 80% and the usage rate of the first-type dopedrows is 20%, the second adjusting operation may change 20% of the logiccells (e.g. the logic cells with the cell structure 306) in thesecond-type doped rows into the logic cells with the cell structure 308.After the second adjusting operation, the usage rate of the second-typedoped rows is changed to 60% from 80% and the usage rate of thefirst-type doped rows is changed to 40% from 20%. Accordingly, thebalancing of the usage of the first-type doped rows and the second-typedoped rows is improved.

Briefly, the proposed embodiment provides jump-row cell structures andrectilinear cell structures for the multi-height layout system toincrease and to balance the usage density and the placement flexibilityof the multi-height layout system. The resource of the multi-heightlayout system may be increased by placing the rectilinear cellstructures into the rectilinear space fragments. Moreover, the jump-rowlogic cell structures may provide transistors with equal speed such thatthe signal delay of the cell may be balanced and optimized.

In some embodiments, the present disclosure provides a logic cellstructure embodied on a non-transitory computer-readable medium. Thelogic cell structure comprises a first portion, a second portion, and athird portion. The first portion is arranged to be a first layout of afirst semiconductor element. The logic cell structure is formed on asubstrate area. As viewed from a top of the substrate area, the firstportion is placed in a first cell row of the substrate area, the firstcell row extends in a first direction, and the first portion has a firstheight in a second direction vertical to the first direction. The secondportion is arranged to be a second layout of a second semiconductorelement. As viewed from the top of the substrate area, the secondportion is placed in a second cell row of the substrate area and has thefirst height in the second direction, and the first portion is separatedfrom the second portion. The third portion is arranged to be a thirdlayout of an interconnecting path used for coupling the firstsemiconductor element and the second semiconductor element. As viewedfrom the top of the substrate area, the third portion is placed withinthe substrate area, and the first portion, the second portion, and thethird portion are bounded by a bounding box with a height in the seconddirection and a width in the first direction. A center of the firstportion and a center of the second portion are arranged in a thirddirection different from each of the first direction and the seconddirection.

In some embodiments, the present disclosure provides an integratedcircuit. The integrated circuit comprises a substrate area, a firstlogic cell and a second logic cell. The substrate area comprises aplurality of first-type doped rows and a plurality of second-type dopedrows. As viewed from a top of the substrate area, each of the first-typedoped rows extends in a first direction, and has a first height in asecond direction vertical to the first direction. The second-type dopedrows are interleaved with the first-type doped rows. As viewed from thetop of the substrate area, each of the second-type doped rows extends inthe first direction, and has a second height in the second direction.The first logic cell, formed on the substrate area, comprises a firstportion, a second portion and a third portion. As viewed from the top ofthe substrate area, the first portion has the first height in the seconddirection and placed in one of the first-type doped rows, the secondportion is placed in one of the second-type doped rows disposed at oneside of the one of the first-type doped rows, and the third portion isplaced in another of the second-type doped rows disposed at another sideof the one of the first-type doped rows. As viewed from the top of thesubstrate area, at least a portion of the second logic cell is placed inone of the one of the first-type rows and the one of the second-typedoped rows.

In some embodiments, the present disclosure provides an integratedcircuit. The integrated circuit comprises a substrate area and a logiccell. The substrate area comprises a plurality of first-type doped rowsand a plurality of second-type doped rows. As viewed from a top of thesubstrate area, each of the first-type doped rows extends in a firstdirection, and has a first height in a second direction vertical to thefirst direction. The second-type doped rows are interleaved with thefirst-type doped rows. As viewed from the top of the substrate area,each of the second-type doped rows extends in the first direction, andhas a second height in the second direction. The logic cell, formed onthe substrate area, comprises a first portion, a second portion and athird portion. As viewed from the top of the substrate area, each of thefirst portion and the second portion has the first height in the seconddirection, the first portion is placed in one of the first-type dopedrows, the second portion is placed in another of the first-type dopedrows, and the third portion is overlapped with two of the second-typedoped rows, disposed at opposite sides of the one of the first-typedoped rows respectively.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A logic cell structure embodied on anon-transitory computer-readable medium, the logic cell structurecomprising: a first portion arranged to be a first layout of a firstsemiconductor element, wherein the logic cell structure is formed on asubstrate area; as viewed from a top of the substrate area, the firstportion is placed in a first cell row of the substrate area, the firstcell row extends in a first direction, and the first portion has a firstheight in a second direction vertical to the first direction; a secondportion arranged to be a second layout of a second semiconductorelement, wherein as viewed from the top of the substrate area, thesecond portion is placed in a second cell row of the substrate area andhas the first height in the second direction, and the first portion isseparated from the second portion; and a third portion, arranged to be athird layout of an interconnecting path used for coupling the firstsemiconductor element and the second semiconductor element, wherein asviewed from the top of the substrate area, the third portion is placedwithin the substrate area, and the first portion, the second portion andthe third portion are bounded by a bounding box with a height in thesecond direction and a width in the first direction; a center of thefirst portion and a center of the second portion are arranged in a thirddirection different from each of the first direction and the seconddirection.
 2. The logic cell structure of claim 1, wherein the thirddirection is a diagonal direction of the bounding box.
 3. The logic cellstructure of claim 1, wherein the third portion has a second height inthe second direction, and the second height is different from the firstheight.
 4. The logic cell structure of claim 1, wherein the thirdportion has the first height in the second direction.
 5. The logic cellstructure of claim 1, wherein an operating speed of a transistorincluded in the first semiconductor element formed according to thefirst portion is equal to an operating speed of a transistor included inthe second semiconductor element formed according to the second portion.6. The logic cell structure of claim 1, wherein the first portion andthe second portion are located at opposite sides of the third portion inthe second direction; the height of the bounding box is equal to orgreater than a total of the first height of the first portion, the firstheight of the second portion, and a distance between the first portionand the second portion in the second direction.
 7. The logic cellstructure of claim 1, wherein the first portion and the second portionare located at opposite sides of the third portion in the seconddirection; the width of the bounding box is equal to or greater than atotal of a first width of the first portion, a second width of thesecond portion, and a distance between the first portion and the secondportion in the first direction.
 8. An integrated circuit, comprising: asubstrate area, comprising: a plurality of first-type doped rows,wherein as viewed from a top of the substrate area, each of thefirst-type doped rows extends in a first direction, and has a firstheight in a second direction vertical to the first direction; and aplurality of second-type doped rows, interleaved with the first-typedoped rows, wherein as viewed from the top of the substrate area, eachof the second-type doped rows extends in the first direction, and has asecond height in the second direction; a first logic cell, formed on thesubstrate area, the first logic cell comprising: a first portion, asecond portion and a third portion, wherein as viewed from the top ofthe substrate area, the first portion has the first height in the seconddirection and placed in one of the first-type doped rows, the secondportion is placed in one of the second-type doped rows disposed at oneside of the one of the first-type doped rows, and the third portion isplaced in another of the second-type doped rows disposed at another sideof the one of the first-type doped rows; and a second logic cell,wherein as viewed from the top of the substrate area, at least a portionof the second logic cell is placed in one of the one of the first-typerows and the one of the second-type doped rows.
 9. The integratedcircuit of claim 8, wherein another portion of the second logic cell isplaced in the other of the one of the first-type rows and the one of thesecond-type doped rows.
 10. The integrated circuit of claim 8, whereinanother portion of the second logic cell is placed in another of thefirst-type doped rows.
 11. The integrated circuit of claim 8, whereinthe second height is different from the first height.
 12. The integratedcircuit of claim 8, wherein the second height is equal to the firstheight.
 13. The integrated circuit of claim 8, wherein a center of thefirst portion and a center of the second portion are arranged in a thirddirection different from each of the first direction and the seconddirection.
 14. The integrated circuit of claim 8, wherein as viewed fromthe top of the substrate area, the portion of the second logic cell isoverlapped with one of the first portion and the second portion.
 15. Anintegrated circuit, comprising: a substrate area, comprising: aplurality of first-type doped rows, wherein as viewed from a top of thesubstrate area, each of the first-type doped rows extends in a firstdirection, and has a first height in a second direction vertical to thefirst direction; and a plurality of second-type doped rows, interleavedwith the first-type doped rows, wherein as viewed from the top of thesubstrate area, each of the second-type doped rows extends in the firstdirection, and has a second height in the second direction; and a logiccell, formed on the substrate area, the logic cell comprising: a firstportion, a second portion and a third portion, wherein as viewed fromthe top of the substrate area, each of the first portion and the secondportion has the first height in the second direction, the first portionis placed in one of the first-type doped rows, the second portion isplaced in another of the first-type doped rows, and the third portion isoverlapped with two of the second-type doped rows, disposed at oppositesides of the one of the first-type doped rows respectively.
 16. Theintegrated circuit of claim 15, wherein the third portion is furtheroverlapped with the one of the first-type doped rows.
 17. The integratedcircuit of claim 15, wherein the third portion is further overlappedwith the another of the first-type doped rows.
 18. The integratedcircuit of claim 15, wherein a center of the first portion and a centerof the second portion are arranged in a third direction different fromeach of the first direction and the second direction.
 19. The integratedcircuit of claim 15, wherein the second height is different from thefirst height.
 20. The integrated circuit of claim 15, wherein the secondheight is equal to the first height.